1. Field of the Invention
The present invention generally rleates to a logic analyzer. More particularly, the invention concerns such a type of logic analyzer which includes a plurality of sampling channels adapted to sample data with different clocks independent of one another and which can display sequential relationships in time among the sampled data.
2. Description of the Prior Art
The logic anaylzer is a sort of measuring instrument which is designed to sample input data with a clock pulse signal of a predetermined frequency and display the sampled data in the form of waveforms, list or the like.
Recently, there has been developed a logic analyzer which incorporates a plurality of sampling channels adapted to operate with respective clocks independent of one another.
FIG. 1 of the accompanying drawings shows schematically a circuit configuration of a sampling channel. In the figure, a reference symbol 1A denotes a data latch, 1B a sampling circuit, 1C a memory, and 1D an address counter. These elements 1A to 1D cooperate to constitute one sampling channel of a logic analyzer. Input data is supplied to a terminal 3A, while a clock pulse signal is applied to a terminal 4A from an internal or external sampling clock source.
The input data also denoted by 3A in inputted to the data latch 1A and sampled by the sampling circuit 1B with the clock pulse signal 4A, the sampled data being stored in the memory 1C. At that time, the address counter 1D is simultaneously incremented in response to the clock pulse 4A to designate the address of the memory 1C where the sampled data is to be stored.
FIG. 2 of the accompanying drawings shows a circuit configuration in which two sampling channels are employed. In the figure, rference symbols 11C and 11D denote sampling channels, respectively, 3A and 3B iput data, and 4A and 4B clock pulse signals, respectively. It should be understood that each of the sampling channels 11C and 11D includes the components 1A to 1D described above. Since the clock signals 4A and 4B ar ordinarily asynchronous with each other, the sequential relationship between the input data 3A of the sampling channel 11C and the input data 3B of the sampling channel 11D can not be determined. In other words, although the sequence in which the data is sampled in each sampling channel can be determined, the relationship in time between the different sampling channels can not be recognized. Consequently, difficulty is encountered in analyzing the relationship between the data signals processed with different clocks.